Module core::arch::aarch64

Available on AArch64 or target_arch="arm64ec" only.

Platform-specific intrinsics for the aarch64 platform.

See the module documentation for more details.

Structs

• SYExperimental
  Full system is the required shareability domain, reads and writes are the required access types

Constants

• _PREFETCH_LOCALITY0Experimental
  See prefetch.
• _PREFETCH_LOCALITY1Experimental
  See prefetch.
• _PREFETCH_LOCALITY2Experimental
  See prefetch.
• _PREFETCH_LOCALITY3Experimental
  See prefetch.
• _PREFETCH_READExperimental
  See prefetch.
• _PREFETCH_WRITEExperimental
  See prefetch.
• _TMFAILURE_CNCLExperimental
  Transaction executed a TCANCEL instruction
• _TMFAILURE_DBGExperimental
  Transaction aborted due to a debug trap.
• _TMFAILURE_ERRExperimental
  Transaction aborted because a non-permissible operation was attempted
• _TMFAILURE_IMPExperimental
  Fallback error type for any other reason
• _TMFAILURE_INTExperimental
  Transaction failed from interrupt
• _TMFAILURE_MEMExperimental
  Transaction aborted because a conflict occurred
• _TMFAILURE_NESTExperimental
  Transaction aborted due to transactional nesting level was exceeded
• _TMFAILURE_REASONExperimental
  Extraction mask for failure reason
• _TMFAILURE_RTRYExperimental
  Transaction retry is possible.
• _TMFAILURE_SIZEExperimental
  Transaction aborted due to read or write set limit was exceeded
• _TMFAILURE_TRIVIALExperimental
  Indicates a TRIVIAL version of TM is available
• _TMSTART_SUCCESSExperimental
  Transaction successfully started.

Functions

• __crc32b^⚠Experimentalcrc
  CRC32 single round checksum for bytes (8 bits).
• __crc32cb^⚠Experimentalcrc
  CRC32-C single round checksum for bytes (8 bits).
• __crc32ch^⚠Experimentalcrc
  CRC32-C single round checksum for half words (16 bits).
• __crc32cw^⚠Experimentalcrc
  CRC32-C single round checksum for words (32 bits).
• __crc32h^⚠Experimentalcrc
  CRC32 single round checksum for half words (16 bits).
• __crc32w^⚠Experimentalcrc
  CRC32 single round checksum for words (32 bits).
• __dmb^⚠Experimental
  Generates a DMB (data memory barrier) instruction or equivalent CP15 instruction.
• __dsb^⚠Experimental
  Generates a DSB (data synchronization barrier) instruction or equivalent CP15 instruction.
• __isb^⚠Experimental
  Generates an ISB (instruction synchronization barrier) instruction or equivalent CP15 instruction.
• __nop^⚠Experimental
  Generates an unspecified no-op instruction.
• __sev^⚠Experimental
  Generates a SEV (send a global event) hint instruction.
• __sevl^⚠Experimental
  Generates a send a local event hint instruction.
• __tcancel^⚠Experimentaltme
  Cancels the current transaction and discards all state modifications that were performed transactionally.
• __tcommit^⚠Experimentaltme
  Commits the current transaction. For a nested transaction, the only effect is that the transactional nesting depth is decreased. For an outer transaction, the state modifications performed transactionally are committed to the architectural state.
• __tstart^⚠Experimentaltme
  Starts a new transaction. When the transaction starts successfully the return value is 0. If the transaction fails, all state modifications are discarded and a cause of the failure is encoded in the return value.
• __ttest^⚠Experimentaltme
  Tests if executing inside a transaction. If no transaction is currently executing, the return value is 0. Otherwise, this intrinsic returns the depth of the transaction.
• __wfe^⚠Experimental
  Generates a WFE (wait for event) hint instruction, or nothing.
• __wfi^⚠Experimental
  Generates a WFI (wait for interrupt) hint instruction, or nothing.
• __yield^⚠Experimental
  Generates a YIELD hint instruction.
• _prefetch^⚠Experimental
  Fetch the cache line that contains address p using the given RW and LOCALITY.